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12-Gbps Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Dat
提出一种新型高效引脚/能量信号方案——编织时钟信号(BCS)，在12Gbps速率下实现无数据开销的时钟嵌入。
12-Gb/s, 28-nm CMOS, 四线平衡传输
编织时钟信号非归零编码引脚效率时钟嵌入电压裕度
▸编织时钟信号(BCS)技术实现无数据开销的时钟嵌入
▸采用扩展转换方案(STS)降低电磁干扰(EMI)
▸非归零(NRZ)编码确保接收端电压裕度优势
Abstract
This paper presents a new pin/energy-efficient data
and clock signaling scheme, named braid clock signaling (BCS).
This signaling scheme efficiently embeds clock information into
the data stream without data overhead, unnecessary pins, and
channels for clock. To remove the data overhead, the clock
information is embedded in every other data period. This high
transition density (TD) leads to the enhanced jitter tracking
performance of a receiver and increased stability. Furthermore,
a spread transi