A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time

Abstract

Successive approximation register (SAR) analog- to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, ach