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JSSC 2019第2期Data Converters65nmSAR ADCDAC

A 10-b 20-MSs SAR ADC With DAC-Compensated Discrete-Time Reference Driver

提出一种带DAC补偿的离散时间参考驱动器的10位20MS/s SAR ADC，降低功耗和面积。
10-bit, 20MS/s, 65nm CMOS
SAR ADC参考驱动器DAC补偿离散时间电荷再分配
▸集成低功耗、面积高效的离散时间参考驱动器
▸通过辅助DAC阵列补偿参考电压下降和码依赖的非二进制DAC切换步骤
▸利用冗余技术进一步减少参考电压下降的影响
Abstract
Successive approximation register (SAR) analog- to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively