JSSC 2019第2期RF & Wireless65nmPLL

A 37-mW 24-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation

一种基于BBPLL的低功耗24GHz GFSK接收器，采用1位相位数字转换技术

65nm CMOS, 0.8V, 100kb/s, -89dBm灵敏度, 3.7mW功耗

低功耗BBPLLGFSK解调相位数字转换温度稳定

▸使用无分频器的BBPLL实现1位过采样噪声整形解调

▸双路径LC VCO设计以适应温度变化

▸环形VCO提供独立的增益控制和低通滤波

Abstract

This paper describes a low-power phase-domain receiver with single-bit phase-to-digital conversion by utilizing a divider-less bang-bang phase-locked loop (BBPLL). The BBPLL performs 1-bit oversampled noise-shaping demodulation as a secondary loop in the receiver, offering a ﬂexible gain control as well as a simple baseband interface. A prototype 2.4-GHz receiver with an auxiliary 50-MHz BBPLL is implemented in 65-nm CMOS. In the RF loop, a dual-path LC voltage-controlled oscillator (VCO) with p