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A 64-Gbps 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET
16nm FinFET工艺的64Gbps 4-PAM收发器，采用自适应阈值ADC优化功耗与误码率。
16nm FinFET, 1.2V, 64Gbps, 1.39pJ/bit, BER<1e-6
4-PAMFinFET自适应ADC贪婪搜索非均匀量化
▸自适应阈值ADC通过贪婪搜索优化非均匀量化
▸功耗随链路损耗动态调整
▸三抽头FFE实现高精度信号调制
Abstract
A 64-Gb/s 4-pulse-amplitude modulation (PAM)
transceiver fabricated with a 16-nm fin field effect transistor
(FinFET) technology is presented with a power consumption
that scales with link loss. The transmitter (TX) includes a
three-tap feed-forward equalizer (FFE) (one pre and one post)
achieving a level separation mismatch ratio (RLM) of 99% and
a random jitter (RJ) of 162-fs rms. The maximum swing is
1.1 V
ppd at a power consumption of 89.7 mW including clock
distribution from a 1.2-V supply, c