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A 7T-SRAM With Data-Write Technique by Capacitive Coupling
提出一种通过电容耦合写入数据的7T-SRAM，解决电流冲突问题并提升稳定性。
24nm 3.3V CMOS, 1.5V/1.8V Vdd, 20ns/10ns cycle time, 18ns/10ns access time, 400 FIT/Mb SER
7T-SRAM电容耦合静态噪声容限阈值电压变化非易失性存储器
▸采用电容耦合写入数据，消除传统读写端口的电流冲突问题
▸通过大耦合晶体管设计增强写入差分信号，适应阈值电压变化
▸7T-SRAM单元面积与6T-SRAM相当，比8T-SRAM小10%
Abstract
A 7-transistor static random access memory
(SRAM), in which cell data are written by capacitive coupling,
is proposed. In the 7T-SRAM configuration, the traditional
read/write port using two pass-gates (PGs), which are used
in 6T-SRAM, is eliminated and the read port using two transistors
such as 8T-SRAM and the equalizer for the cell node pair
are installed. This read port transistor also acts as a coupling
capacitor for writing external data after floating paired cell nodes.
The elimination of c