JSSC 2019第2期Data Converters28nmPipeline ADC

A Single-Channel 600-MSs 12-b Ringamp-Based Pipelined ADC in 28-nm CMOS

28nm CMOS工艺下基于环形放大器的600MS/s 12位流水线ADC设计

28nm CMOS, 0.9V, 600MS/s, 58.7dB SNDR, 72.4dB SFDR, 14.5mW

流水线ADC环形放大器低电压设计高速转换器纳米级CMOS

▸利用环形放大器的低但稳定的开环增益特性实现高速高线性度

▸采用反并联CMOS晶体管可调偏置方案

▸基于环形放大器的主动共模反馈技术

Abstract

Achieving high linearity and bandwidth with good power efﬁciency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introduc- ing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring ampliﬁer (ringamp) to a