JSSC 2019第2期Other65nm

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Tim

一种用于统计表征CMOS晶体管变异性的多功能阵列芯片。

1.2-V, 65-nm CMOS, 3136 MOS transistors, 1800 × 1800 µm²

CMOS晶体管阵列统计表征时间零点变异随机电报噪声偏置温度不稳定性

▸集成3136个MOS晶体管，支持多种变异源统计表征

▸支持大规模并行老化测试，显著缩短统计表征时间

▸高精度测试架构，满足多种变异效应表征需求

Abstract

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias tempera- ture instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with ei