An 821076-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Pa

Abstract

A W-band integer-N all-digital phase-locked loop (ADPLL) aiming for wide frequency tuning range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally controlled oscillator (DCO) with split transformer and dual-path exponentially scaled switched-capacitor ladder and a clock-skew- sampling delta–sigma time-to-digital converter (TDC). The 65-nm CMOS W-band ADPLL measures a frequency TR of 27% from 82 to 107.6 GHz and phase noise from −106 to −110 dBc/Hz at 10-MHz offset and −84