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High-Linearity Bottom-Plate Mixing Technique With Switch Sharing for N-path Filters/Mixers
提出一种高线性度底极板混频技术,用于SAW-less FDD接收机,实现低噪声和高线性度。
28nm CMOS, +44 dBm OOB IIP3, +90 dBm IIP2, +13 dBm 1-dB压缩点, 38-96 mW功耗
底极板混频开关共享四路径滤波器高线性度SAW-less接收机
▸底极板混频技术提高线性度
▸差分底极板混频实现开关共享
▸交叉耦合开关-RC四路径级提供低阻高线性电流路径
Abstract
A four-path filter/mixer for surface acoustic wave (SA W)-less frequency division duplex (FDD) radio receivers is proposed, targeting high linearity and compression require- ments. A bottom-plate mixing technique improves linearity by reducing the gate-source voltage modulation of the MOSFET switches. Differential bottom-plate mixing allows for switch sharing which halves the effective switch resistance to reduce drain-source voltage modulation. The first four-path switch-RC filter stage with bottom-plate mixing and a shared switch renders 2nd-order voltage-domain RF-bandpass filtering around the LO frequency. Extra out-of-band rejection is implemented combined with V–I conversion and zero-IF frequency down-conversion in the second cross-coupled switch-RC four-path stage, which offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28-nm CMOS technology achieves an out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset fre- quency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7-GHz LO (i.e., 6- and 9-dB blocker noise figure). The chip consumes 38–96 mW for LO-frequencies of 0.1–2 GHz and occupies an active area of 0.49 mm 2.