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Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS
提出一种18晶体管全静态无竞争单相时钟触发器，实现低功耗和面积优化。
65nm CMOS, 0.6V, 25°C
触发器低功耗单相时钟静态设计CMOS
▸创新点1：提出了一种仅使用18个晶体管的完全静态无竞争单相时钟触发器（18TSPC），这是此类触发器中最少的晶体管数量，显著降低了电路复杂度（电路创新）。
▸创新点2：在65nm CMOS工艺下实现，与传统的传输门触发器（TGFF）相比，18TSPC的单元面积减少了20%，优化了芯片布局（电路创新）。
▸创新点3：仿真结果表明，18TSPC在能量-延迟空间中的效率是TGFF的两倍，显著提升了能效比（性能创新）。
▸创新点4：实验测量显示，在0.6V、25°C条件下，18TSPC相比TGFF整体动态功耗降低了68%，时钟动态功耗降低了73%，泄漏功耗减少了27%，进一步验证了其低功耗特性（性能创新）。
Abstract
Flip-flops (FFs) are essential building blocks of sequential digital circuits but typically occupy a substantial proportion of chip area and consume significant amounts of power. This paper proposes 18-transistor single-phase clocked (18TSPC), a new topology of fully static contention-free single- phase clocked (SPC) FF with only 18 transistors, the lowest number reported for this type. Implemented in 65-nm CMOS, it achieves 20% cell area reduction compared to the conven- tional transmission gate FF (TGFF). Simulation results show the proposed 18TSPC is two times more efficient than TGFF in the energy-delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6 V , 25 ◦Cs h o wt h a t ,c o m p a r e dt oT G F F , the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.