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A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
采用死区退化和第二级偏置增强技术的12位1GS/s流水线ADC，在28nm CMOS工艺下实现高性能。
28nm CMOS, 0.9V, 1GS/s, 56.6dB SNDR, 73.1dB SFDR, 24.8mW
流水线ADC环形放大器死区退化高速转换器低功耗设计
▸创新点1：死区退化技术(DZD)通过优化环形放大器的线性度，显著提高了ADC的信噪比(SNDR)和无杂散动态范围(SFDR)，分别达到56.6 dB和73.1 dB。
▸创新点2：第二级偏置增强技术通过提升环形放大器的偏置电流，进一步扩展了其工作带宽，使ADC能够在1 GS/s的高采样率下稳定运行。
▸创新点3：环形放大器的高线性度与带宽优化结合了低电压深纳米CMOS工艺的优势，实现了高线性度和高带宽的同时，保持了良好的功率效率，功耗仅为24.8 mW。
▸创新点4：该ADC在28-nm平面CMOS工艺中实现，通过创新的电路设计和方法优化，达到了159.6 dB的Schreier FoM和45 fJ/conv.-step的Walden FoM，展示了卓越的性能指标。
Abstract
Ring amplification has recently been shown capa- ble of simultaneously achieving high linearity and high band- width (BW) in low-voltage, deep nanoscale CMOS processes, while retaining good power efficiency. In these processes, the low but very flat open-loop (OL) gain versus output voltage character- istic of the ring amplifier can be exploited, together with its high BW, to overcome the low intrinsic gain limitations that otherwise mandate the use of power-consuming analog circuits and complex digital calibration. Within this context, this paper introduces the techniques of dead-zone degeneration (DZD) and second-stage bias enhancement to further extend the linearity and speed limits of the ring amplifier, respectively. These techniques are applied to a 12-b, 1-GS/s, single-channel pipelined ADC implemented in a 28-nm planar CMOS process, which achieves 56.6-dB SNDR and 73.1-dB SFDR while consuming 24.8 mW from a single 0.9-V supply, resulting in Schreier and Walden figure-of- merit (FoM) values of 159.6 dB and 45 fJ/conv.-step, respectively.