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A 15-Gbps Sub-Baud-Rate Digital CDR
一种采用亚波特率时钟的15Gbps数字CDR电路，利用四分之一速率时钟实现高效数据恢复。
65nm CMOS, 15.2Gb/s, BER<10^-12, >10MHz JTOL, 548fs rms抖动, 29mW功耗, 1.9pJ/bit能效
时钟数据恢复亚波特率数字CDR背景校准线性均衡器
▸使用差分四分之一速率时钟恢复时钟和数据
▸八采样器与积分器结合实现每周期四位数据恢复
▸采样器复用实现相位检测和背景校准
Abstract
This paper presents a sub-baud-rate clock and data
recovery (CDR) circuit that can recover clock and data using only
differential quarter-rate clocks. A combination of eight samplers
and an integrator recover four data bits in each clock cycle. Four
of the eight samplers are re-used for phase detection as well as for
background calibration to improve the robustness of the CDR
to process, voltage, and temperature variations. A continuous-
time linear equalizer is used to compensate for inter-symb