A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS Laszlo Szilagyi , Jan Pliva, Ronny Henker , David Schoeniger

Abstract

This paper demonstrates a receiver (RX) for optical communications implemented in a 28-nm digital bulk-CMOS technology. Compact bandwidth (BW)-enhancement methods, such as inductor sharing and stacking, result in a measured BW of 27 GHz. By using these area-efficient techniques and a mixed-signal offset compensation system, a small active area of 0.009 mm 2 is achieved. Noise and jitter are analyzed for the transimpedance amplifier and the limiting amplifier. Operation up to a data rate (DR) of 54 Gbit/s is demonstrated electrically with an energy efficiency of 0.6 pJ/bit. A commercial, 25-Gbit/s photo-diode (PD) is wire-bonded to the RX chip on a printed circuit board (PCB) assembly. Error-free (BER < 10 −12)o p t i c a l transmission at 53 Gbit/s is achieved with a transmitter (TX) using a 35-GHz electro-optical modulator. At this DR, an energy- per-bit of 0.65 pJ/bit is measured without the 16.5-mW output buffer, which only serves measurement purposes. An input sensitivity of −6-dBm optical modulation amplitude (OMA) is measured at 53 Gbit/s. Power/DR adaptivity is featured by the design; so when the DR can be reduced, the power consumption is decreased in order to maintain the energy efficiency. Energy- per-bit is improved from 1.28 pJ/bit by 52% to 0.67 pJ/bit at 27 Gbit/s.