JSSC 2019第3期RF & Wireless28nmTime-Interleaved ADC

A 56-GSps 8-bit Time-Interleaved ADC

本文介绍了一种56GS/s时间交织ADC，采用多种技术提升带宽和ENOB。

28nm CMOS, 56GS/s, 5.7-b ENOB, 31.5GHz BW

时间交织ADC带宽增强低噪声放大器开关缓冲器CMOS工艺

▸创新点1：低噪声参数T/H放大器，采用参数放大技术，显著提升采样信号的信噪比（SNR），为后续子通道ADC提供更清晰的信号输入。

▸创新点2：开关子通道缓冲器，通过动态切换缓冲器，有效避免了跟踪过程中因缓冲器带宽限制导致的信号失真问题。

▸创新点3：多种带宽增强技术，结合电路优化和系统级设计，将ADC的带宽扩展至31.5 GHz，满足100/200 Gb/s数字相干接收器的需求。

▸创新点4：28nm CMOS工艺实现，在0.878 mm²的芯片面积内集成高性能ADC，功耗仅为702 mW，展现了高集成度和能效优势。

Abstract

This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-digital converter (ADC) with 5.7-b effective number of bits (ENOB) and 5.2-b ENOB up to 17.5 and 27.1 GHz, respectively. To achieve the ENOB requirement over the entire Nyquist BW in 100-/200-Gb/s digital coherent receivers, several ENOB and BW enhancement tech- niques are presented. First, a low-noise parametric T/H ampliﬁer is proposed to amplify the sampled signal and improve the SNR of the subsequent sub-ch