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A Low-Noise Fractional- N Digital Frequency Synthesizer
提出一种60GHz分数-N数字频率合成器，降低相位噪声并优化功耗。
213–277fs RMS抖动，57.5–67.2GHz调谐范围，40mW功耗
毫米波频率合成器相位噪声数字锁相环CMOS
▸利用20GHz DCO产生60GHz三次谐波
▸采用全数字锁相环结构降低闪烁噪声
▸数字-时间转换器与时间-数字转换器组合抑制分数杂散
Abstract
In this paper, we propose a 60-GHz fractional- N
digital frequency synthesizer aimed at reducing its phase
noise (PN) at both the flicker (1 /f 3) and thermal (1 /f 2)
regions while minimizing its power consumption. The digitally
controlled oscillator (DCO) fundamentally resonates at 20 GHz
and co-generates a strong third harmonic at 60 GHz which is
extracted to the output while canceling the 20-GHz fundamental.
The latter component is fed back to the frequency dividers in an
all-digital phase-lo