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JSSC 2019第4期Other65nm

A 1-mW Class-AB Amplifier With −101 dB THD+N for High-Fidelity 16  Headphones in 65-nm CMOS

一款用于高保真耳机的低功耗AB类放大器,实现-101.4dB THD+N和0.97mW静态功耗。
65nm CMOS, 0.97mW静态功耗, -101.4dB THD+N, 12.3MHz UGB, 108dB SNR, 51.2mW峰值功率
AB类放大器高保真耳机低功耗THD+NCMOS
级联驱动网状技术限制输出级高摆幅节点数量
频率补偿方案扩展单位增益带宽和20kHz环路增益
结合两种技术实现超低非线性失真
Abstract
A low-power class-AB amplifier for high-fidelity headphones is presented. The linearity of a class-AB amplifier strongly depends on the loop gain over the audio band and voltage swing. In this paper, a cascode-driven mesh technique limits the number of high-swing nodes in the output stage, thereby preserving the loop gain of the preceding gain stages. A frequency compensation scheme is proposed that extends the unity-gain bandwidth (UGB) and increases the loop gain at 20 kHz. Combining these two techniques, the amplifier achieves −101.4-dB total harmonic distortion plus noise (THD +N) over the full audio band, the lowest ever reported nonlinearity among sub-milliwatt CMOS class-AB amplifiers. The amplifier delivers 51.2-mW peak power to a 16 0.33-nF load while consuming 0.97 mW of total static power. It has UGB of 12.3 MHz and SNR of 108 dB. These results are consistent when measured over eight test chips. Compared to the recent prior art, the amplifier exhibits >12 dB better linearity and >14-dB dynamic range. This results in 2.5 × improvement in figure of merit (FOM = Peak Load Power/(Quiescent Power × THD+N[%])). It occupies 0.16 mm 2 in a standard 65-nm CMOS.