A 290-mV , 7-nm Ultra-Low-V oltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

Abstract

In this paper, we present an ultra-low voltage one- port static random access memory (SRAM) compiler target- ing small to medium array sizes to provide a smaller area solution compared to conventional 6T-based SRAMs. A 12T write contention and read upset free bit-cell are used in the design. Array architecture employs a read–modify–write scheme to support bit-write (BW) masking and column multiplexing. Built-in-self-test (BIST) and syn chronous write-through (SWT) options are also supported to provide testability features, while power management (PM) option is included to provide low- leakage sleep and shut-down modes. The proposed design is fabricated in 7-nm FinFET technology and achieves the lowest reported V min of 290 mV in this technology.