A 550-μW 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental  ADC With 256 Clock Cycles in 65-nm CMOS

Abstract

This paper presents an incremental analog-to- digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal- to-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform- exponential weight function allows the data weighted averag- ing (DW A) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to sup- press the line noise. Implemented in 65-nm CMOS under 1.2- V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 µW, and 0.134 mm 2, resulting in Walden/Schreier FoM W/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral non- linearities are +0.27 LSB/−0.27 LSB and +0.84 LSB/−0.81 LSB, respectively.