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A 550-μ W 20-kHz BW 1008-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ AD
提出一种两阶段线性-指数累积环路的增量型模数转换器，结合线性阶段的噪声抑制和指数阶段的SQNR提升。
65nm CMOS, 1.2V, 20kHz BW, 100.8dB SNDR, 550μW
增量型模数转换器线性-指数累积噪声耦合数据加权平均信号量化噪声比
▸两阶段线性-指数累积环路设计
▸噪声耦合路径提升信号量化噪声比
▸均匀指数权重函数支持数据加权平均技术
Abstract
This paper presents an incremental analog-to-
digital converter (IADC) with a two-phase linear-exponential
accumulation loop. In the linear phase, the loop works as
a first-order structure. The noise-coupling (NC) path is then
enabled in the exponential phase thus boosting the signal-
to-quantization-noise ratio (SQNR) exponentially with a few
number of clock cycles. The two-phase scheme combines the
advantages of the thermal noise suppression in the first-order
IADC and SQNR boosting in the expon