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A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement
提出一种次谐波开关数字功放架构，提升功率回退区效率
26.8-dBm峰值输出功率，49.3%峰值漏极效率(DE)，-13dB PBO时27% DE
次谐波开关数字功放功率回退效率提升CMOS
▸创新点1：次谐波开关(SHS)技术（方法创新） - 提出一种新型次谐波开关架构，通过在功率回退(PBO)区域动态调整开关频率，显著提升效率。实验显示在-13dB PBO时仍保持27%的漏极效率。
▸创新点2：双模式协同优化（系统创新） - 创新性地结合SHS与class-G双电源切换技术，通过智能模式选择算法在不同功率级别自动切换最优工作模式，实现四个峰值效率点(0/-3.5/-9.5/-13dB)。
▸创新点3：混合型SCPA电路设计（电路创新） - 在65nm CMOS工艺中实现开关电容功率放大器(SCPA)与SHS的混合架构，通过电容阵列重构技术兼顾高频(2.25GHz)和大功率(26.8dBm)特性。
▸创新点4：多级效率优化策略（方法创新） - 提出分级功率回退效率增强方案，通过子单元独立控制实现峰间效率平滑过渡，较传统PA在-6dB PBO区域效率提升40%以上。
Abstract
This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, −3.5, −9.5, and, −13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at −13-dB PBO.