JSSC 2019第5期Clocking & PLLs65nmPLL

A 24-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-N

一种新型24GHz参考采样锁相环，同时实现低噪声和低杂散性能。

65nm CMOS, 2.05-2.55GHz, 抖动功率优值<-251dB, 参考杂散<-66dBc@50MHz

锁相环参考采样低噪声低杂散时钟乘法器

▸采用参考采样锁相环（RS-PLL）结构，通过VCO方波采样参考正弦波来估计相位误差

▸使用时钟隔离缓冲器替代传统参考缓冲器，将采样时钟缓冲和VCO隔离功能集成到单一模块

▸限制开关电路在参考信号过零区域活动，降低VCO频率采样的功耗

Abstract

Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-locked clock multipli- ers have demonstrated some of the lowest jitters for a given power consumption (jitter-power FoM j metric). However, they contain a tradeoff between the spur and noise performance, where techniques incorporated for spur reduction adversely affect jitter or power performance. A new dividerless Type-I sampling PLL, called the reference sampling PLL (RS-PLL), which estimates the voltage-cont