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A 28-nm 75-fs rms Analog Fractional- N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty
28纳米工艺下实现75飞秒抖动的高线性DTC模拟分数N采样PLL
28nm CMOS, 75-fs rms抖动, -249.7-dB FoM, 18.9 mW功耗
分数N采样PLL数字时间转换器相位噪声5G毫米波CMOS
▸基于DTC的采样PLL架构：该方法创新通过数字时间转换器（DTC）实现采样PLL架构，显著降低了相位噪声和抖动，实现了75-fs rms抖动和-249.7-dB FoM的高性能指标，适用于5G毫米波通信系统。
▸高线性度DTC设计技术：该电路创新通过优化DTC的线性度，减少了非线性引入的杂散，使得在5.5-7.3 GHz输出频带内测量到的分数杂散低于-64 dBc，提升了系统的整体性能。
▸背景DTC增益校准：该系统创新通过背景DTC增益校准技术，动态调整DTC增益，有效抑制了增益漂移对系统稳定性的影响，进一步降低了相位噪声和抖动，提高了PLL的长期稳定性。
▸参考时钟占空比校正（DCC）：该电路创新通过引入参考时钟占空比校正技术，优化了时钟信号的占空比，减少了时钟抖动，从而提升了PLL的整体性能，支持5G 64-QAM调制标准。
Abstract
An analog fractional- N sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- N mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital- to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain cali- bration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellu- lar 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting 2 × 2 multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm 2.