JSSC 2019第5期Digital Circuits65nmNeural Network Accelerator

A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

65nm CMOS工艺下实现的40GHz带宽镜像共源共栅差分跨阻放大器

54dBΩ跨阻增益/40GHz带宽/19.8pA/√Hz噪声密度/55.2mW功耗/32Gb/s PRBS眼图

跨阻放大器CMOS差分信号带宽扩展光通信

▸创新点1：镜像共源共栅(MC)输入配置是一种电路创新，通过NMOS共源共栅放大器与交流耦合电容的镜像结构实现差分信号处理，显著提高了信号对称性和噪声抑制能力，支持40-GHz带宽。

▸创新点2：三阶非对称变压器带宽扩展技术属于方法创新，通过精心设计的非对称变压器结构有效扩展了带宽，使TIA在50-fF光电二极管电容下仍能实现40-GHz的高带宽性能。

▸创新点3：全差分结构设计是系统创新，通过完全差分信号路径设计，提高了共模噪声抑制能力，同时实现了54-dBΩ的跨阻增益和±10-ps的群延迟变化，优化了高速信号完整性。

▸创新点4：低噪声设计技术，通过优化输入级和反馈网络，实现了19.8-pA/√Hz的平均噪声电流谱密度，显著提升了接收机的灵敏度。

Abstract

This paper presents a fully differential transim- pedance ampliﬁer (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input conﬁgura- tion is proposed for differential signaling, i.e., an NMOS cascode ampliﬁer with a resistive feedback for negative output and its MC ampliﬁer via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB /Omega1transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA/ √ Hz average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye dia- grams for 32 Gb/s 215−1 pseudo random binary sequence (PRBS) were measured with the input currents of 100–1.5 mApp. The chip occupies the area of 0.6 mm 2 including I/O pads.