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A Dynamic Power Reduction Technique for Incremental Delta Sigma Modulators
提出一种动态功耗降低技术，应用于增量Delta Sigma调制器，通过增加非理想性节省功耗。
180nm CMOS, 3V, 200kS/s, 91.5/86.6 dB SNDR, 1.1mW
增量Delta Sigma调制器动态功耗降低数字重构滤波器多比特DACSQNR
▸利用数字重构滤波器的不等权重降低功耗
▸动态增加第一积分器的输入噪声提高效率
▸运行时切换单比特DAC为多比特DAC提升SQNR
Abstract
This paper presents a dynamic power reduction
technique for incremental /Delta1/Sigma1(I-/Delta1/Sigma1) modulators. The technique
makes use of the unequal weighting of the digital reconstruction
filter. The underlying idea is that the input signal samples are not
equally weighted in the higher order reconstruction filter. Thus,
it is possible to increase the non-idealities of the I- /Delta1/Sigma1modulator
during the runtime of a single Nyquist conversion, thereby
saving power. This principal ide