Secure Satellite Communication Digital IF CMOS Q-Band Transmitter and K -Band Receiver

Abstract

This paper reports the first CMOS RF integrated chipset for secure commercial and military satellite communica- tion enabling next-generation low size, weight, and power (SWaP) terminals. This chipset is a significant departure from current terminals relying on individually qualified IC components by taking advantage of advanced CMOS integration. The transmit- ter and receiver designs are digital IF architectures that rely on the higher sampling rate capability of CMOS, and precise digital filtering, quadrature frequency translation, and frequency hopping/de-hopping. The CMOS transmitter is a fully integrated system-on-chip (SoC) design, while the receiver consists of a co-designed RF and digital IF receiver. The Tx/Rx uses a 200-/300-MHz double data rate (DDR) interface driving/receiving a complex frequency translator with sub-hertz frequency hopping resolution via on-chip numerically controlled oscillators (NCO). The transmitter includes two 12-b return-to-zero (RZ) digital-to- analog converters (DACs) and quadrature modulator to form a single-sideband (SSB) upconverter achieving >30-dB spur rejection. An RF upconverter with an X2 multiplier drives a 24-dBm Q-band CMOS stacked power amplifier (PA). The RF receiver implements a matched inverter amplifier (IA) followed by a complementary active balun that current drives a passive mixer with a trans-impedance active combiner. The digital IF receiver includes a high-linearity variable gain amplifier (VGA) that drives an 8 × time-inter