A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator Sung-En Hsieh and Chih-Cheng Hsieh

Abstract

This paper presents a 13-bit high-resolution two- step analog-to-digital converter (ADC). Successive approximation register (SAR)-ADCs and an incremental sigma-delta modula- tor (ISDM) act as the coarse and fine ADCs, respectively. By using the proposed time-domain ISDM, the integrator is relaxed from the finite gain error and static current consumption. For the matching of the capacitive digital-to-analog converter(CDAC), the integral non-linearity (INL) splitting (INLS) switching proce- dure is developed to reduce the INL and switching energy to 25% and 9% of the reference common-mode voltage (VCM)-based scheme, respectively. With a reduced capacitance of the capacitor array, the requirements of the input driver and reference buffer are effectively relaxed. A prototype was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, which occupies an area of 0.059 mm 2. The achieved spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) at Nyquist rate are 90.38 and 73.57 dB, respectively. The maximum differential non-linearity (DNL) and INL are 0.45 and 0.75 LSB, respectively. The prototype consumes 638 nW at 0.4-V supply and 270-kHz sampling rate. The resultant Schreier figure of merit (FoM) is 186.8 dB, and the Walden FoM is 0.61 fJ/conversion step.