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JSSC 2019第6期Data Converters90nmSAR ADCDelta-Sigma ADC

A 04-V 13-bit 270-kSs SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

提出一种13位高分辨率两步ADC，采用SAR-ADC和ISDM结合，降低功耗和积分器误差。
0.4V, 270kS/s, 90.38dB SFDR, 73.57dB SNDR, 0.45LSB DNL, 0.75LSB INL, 638nW
SAR-ADCISDM时间域积分器INLS切换低功耗
▸时间域ISDM消除积分器增益误差和静态电流
▸INLS切换程序减少INL和切换能量
▸降低电容阵列需求，缓解输入驱动和参考缓冲要求
Abstract
This paper presents a 13-bit high-resolution two- step analog-to-digital converter (ADC). Successive approximation register (SAR)-ADCs and an incremental sigma-delta modula- tor (ISDM) act as the coarse and fine ADCs, respectively. By using the proposed time-domain ISDM, the integrator is relaxed from the finite gain error and static current consumption. For the matching of the capacitive digital-to-analog converter(CDAC), the integral non-linearity (INL) splitting (INLS) switching proce- dure is