A 13.56 MHz, 94.1% Peak Efficiency CMOS Active Rectifier With Adaptive Delay Time Control for Wireless Power

Abstract

In this paper, an adaptive delay time control (ADTC)-based CMOS active rectifier is proposed. Compared with previous active rectifiers, power-hungry comparators are eliminated in this structure. Instead, optimal on/off time of the power switches is generated by two current controlled delay lines (CCDLs), which enables drastic power reduction of the active rectifier. In addition, the multiple-pulsing problem is eliminated due to the introduced control mechanism. The high- precision on/off control at picosecond-level precision removes the reverse current of the rectifier and guarantees high voltage conversion rate (VCR) and power conversion efficiency (PCE). The active rectifier is fabricated with a standard 0.18- µmC M O S process. The experimental results show that the quiescent power consumption of the rectifier is less than 230 µW. The current conduction angle reaches the optimal state under different input and load conditions because of the adaptive adjustment. The peak PCE is 94.1% at the output power of 10.63 mW. The PCE is enhanced by 6.7% compared with the previous design. The maximum output power of 34.1 mW is achieved with input ac amplitude of 2.5 V . The proposed low-power high-efficiency active rectifier gives a favorable solution for the wireless power transmission systems.