← 返回 JSSC 论文列表JSSC 2019第6期Analog Circuits0.18µm CMOS
A 1356 MHz 941x0025 Peak Efficiency CMOS Active Rectifier With Adaptive Delay Ti
提出一种基于自适应延迟时间控制的CMOS有源整流器，显著降低功耗并提升效率。
峰值效率94.1%（输出功率10.63mW时），静态功耗<230µW，最大输出功率34.1mW（输入AC幅值2.5V）
有源整流器自适应延迟控制无线能量传输功率转换效率电流控制延迟线
▸采用自适应延迟时间控制(ADTC)消除功耗较大的比较器
▸使用电流控制延迟线(CCDLs)精确控制开关时间
▸解决多脉冲问题并消除反向电流
Abstract
In this paper, an adaptive delay time control
(ADTC)-based CMOS active rectifier is proposed. Compared
with previous active rectifiers, power-hungry comparators are
eliminated in this structure. Instead, optimal on/off time of the
power switches is generated by two current controlled delay
lines (CCDLs), which enables drastic power reduction of the
active rectifier. In addition, the multiple-pulsing problem is
eliminated due to the introduced control mechanism. The high-
precision on/off control at