← 返回 JSSC 论文列表JSSC 2019第6期Memory65nmNeural Network Accelerator
A 64-Tile 24-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Comp
一款采用电荷域混合信号操作的64片24Mb内存计算CNN加速器，提升计算信噪比和可扩展性。
65nm CMOS, HLs/FL能效866/1.25 TOPS/W, 吞吐量18876/43.2 GOPS
内存计算CNN加速器电荷域操作混合信号DNN
▸电荷域混合信号操作提升计算信噪比和可扩展性
▸支持模拟/二进制输入激活/权重的第一层和二进制/二进制输入激活/权重的隐藏层
▸采用8T位单元与覆盖金属-氧化物-金属电容器的内存计算结构
Abstract
Large-scale matrix-vector multiplications, which
dominate in deep neural networks (DNNs), are limited by data
movement in modern VLSI technologies. This paper addresses
data movement via an in-memory-computing accelerator that
employs charged-domain mixed-signal operation for enhancing
compute SNR and, thus, scalability. The architecture supports
analog/binary input activation (IA)/weight first layer (FL) and
binary/binary IA/weight hidden layers (HLs), with batch nor-
malization and input–output