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JSSC 2019第6期Clocking & PLLs65nm

A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration

一种低抖动、注入锁定的多频率发生器,可在65nm CMOS工艺中独立生成0.9-1.2GHz的多频信号。
960MHz输出信号的1MHz相位噪声-133.5dBc/Hz,rms抖动375fs,面积0.05mm²,功耗7.7mW
低抖动注入锁定多频发生器数字控制振荡器时间交错校准
创新点1:时间交错频率校准器(系统创新) - 该技术通过连续后台操作,实时校准注入锁定DCO的频率,有效对抗PVT变化,确保所有输出信号保持低抖动性能(抖动退化<10%)。
创新点2:独立控制的注入锁定DCO(电路创新) - 每个DCO可独立调节频率(0.9-1.2 GHz,15 MHz步进),实现多频段并发输出,且互不干扰,系统灵活性显著提升。
创新点3:低抖动性能保持(方法创新) - 采用注入锁定技术结合动态校准,在960 MHz输出时实现375 fs超低RMS抖动(1k-40MHz积分)和-133.5 dBc/Hz@1MHz相位噪声。
创新点4:高集成度设计(电路创新) - 在65nm CMOS工艺下实现0.05mm²芯片面积,双频输出功耗仅7.7mW,展现优异的能效比与面积效率。
Abstract
This paper presents a low-jitter, injection-locked frequency generator that can provide multiple output frequencies concurrently. The injection-locked digitally controlled oscilla- tors (DCOs) can be controlled separately so that their output fre- quencies can be changed independently between 0.9 and 1.2 GHz in 15-MHz steps. Due to the proposed time-interleaved frequency calibrator that operates continuously in the background, all injection-locked DCOs are ensured to maintain excellent jitter performance against process, voltage, and temperature (PVT) variations. As a prototype, the proposed injection-locked, multi- frequency generator (ILMFG) was designed to generate two independently controlled output signals, and it was fabricated in a 65-nm CMOS technology. The 1-MHz phase noise and the rms jitter integrated from 1 kHz to 40 MHz of the 960-MHz output signal were −133.5 dBc/Hz and 375 fs, respectively. The degradation of rms jitter was restricted to less than 10%. The silicon area was 0.05 mm 2, and the total power consumption was 7.7 mW when generating two different output frequencies.