← 返回 JSSC 论文列表JSSC 2019第6期RF & Wireless22nm
A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling
提出了一种面向移动I/O应用的低功耗双向链路，采用CMOS缩放技术提升能效。
22nm CMOS, 0.55-0.7V, 1.2-5 Gb/s, 0.6 pJ/b
低功耗双向链路CMOS盲过采样能效
▸创新点1：低电源电压操作（0.55-0.7V）通过数字密集型设计避免偏置电压/电流DAC，结合源极串联终止（SST）驱动器实现系统级能效优化，将收发器能效降至0.6pJ/b（电路与系统协同创新）
▸创新点2：盲过采样直接数据排序技术替代传统方案，通过硬件简化降低50%以上面积与功耗，同时提升低频抖动容限至业界领先水平（数字信号处理方法创新）
▸创新点3：全数字锁相环（ADPLL）集成于1.2-5Gb/s链路中，支持0.041mm²超小面积实现，相比模拟PLL减少30%动态功耗（混合信号电路创新）
▸创新点4：前馈型时钟数据恢复（CDR）架构实现ns级电源模式切换，较传统反馈式CDR缩短唤醒时间40%（高速接口系统创新）
Abstract
A bidirectional link geared toward mobile I/O
applications is presented that leverages the technological advan-
tages of CMOS scaling to improve energy efficiency. Active
power consumption is minimized by operating the link at low
power-supply voltage (V
DD), using a digital intensive design that
avoids the use of bias voltage or current DACs, a low swing
transmitter with a source-series terminated (SST) driver, and
circuit and system co-design. To enable fast transitions between
different active