A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Votin

Abstract

This paper presents a low-power and scaling- friendly noise-shaping (NS) SAR ADC. Instead of using oper- ational transconductance amplifiers that are power hungry and scaling unfriendly, the proposed architecture uses passive switches and capacitors to perform residue integration and realizes the path gains via transistor size ratios inside a multi- path dynamic comparator. The overall architecture is simple and robust. Since the noise transfer function is set by component ratios, it is insensiti