A 135-mW 170TOPS Sparse Video Sequence Inference SoC for Action Classification

Abstract

An inference system-on-chip (SoC) is designed to extract spatio-temporal features from videos for action classifica- tion. The SoC contains an inference core that implements a recur- rent neural network in three processing layers. High sparsity is enforced in each layer of processing, reducing the complexity by two orders of magnitude and allowing multiply accumulates to be replaced by select accumulates. Spatio-temporal kernel and activation compression are applied to reduce memory by 43% and 64