JSSC 2019第7期Data Converters65nmNeural Network Accelerator

A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC

提出一种新型全时间两步ADC，采用高线性度动态延迟器，实现低功耗高性能。

65nm CMOS, 1 GS/s, 2.3 mW, 44.4 dB SNDR

时间基ADC低功耗高线性度动态延迟器两步ADC

▸创新点1：全时间两步ADC结构（方法创新）。该论文提出了一种新型的全时间两步ADC架构，通过将粗ADC（CADC）和细ADC（FADC）以时间为基础的方式流水线化，显著提高了采样频率（1 GHz），同时降低了功耗（23 mW）。这种结构在高速高精度ADC设计中具有显著优势。

▸创新点2：高线性度电压-时间转换器（电路创新）。论文设计了一种高线性度的电压-时间转换器，通过增益控制功能调整CADC和FADC之间的增益差异，确保了宽输入范围和高线性度，从而提升了整体ADC的性能（SNDR 44.4 dB）。

▸创新点3：动态延迟器低功耗设计（电路创新）。采用动态延迟器的插值时间-数字转换器（TDC）设计，通过立即复位STOP信号来阻止无效信号传播，显著降低了功耗（2.3 mW @1 GS/s），同时保持了高转换效率（Walden FoM 16 fJ/conversion step）。

▸创新点4：增益控制功能（系统创新）。通过动态调整CADC和FADC的增益差异，解决了工艺、电压和温度（PVT）变化带来的影响，提升了系统的稳定性和可靠性。

Abstract

A novel fully time-based two-step analog-to-digital converter (ADC) is proposed. Two time-based ADCs (TB ADCs) are used for coarse ADC (CADC) and ﬁne ADC (FADC), result- ing in low-power operation. They are pipelined to increase the sampling frequency. A high-linearity voltage-to-time converter is also proposed to ensure that the CADC has a wide input range. It has a gain-control function to adjust the difference between the gains of the CADC and FADC due to variations in process, voltage and temperature. Moreover, an interpolation time-to-digital converter with a dynamic delayer enables low- power operation. The dynamic delayer is immediately reset when a STOP signal is activated to prevent waste-signal propagation. An 8-bit test chip fabricated with the 65-nm CMOS technology consumed 2.3 mW at 1 GS/s. It also had a sufﬁciently high signal-to-noise and distortion ratio (SNDR) of 44.4 dB even at the Nyquist frequency. It had a Walden ﬁgure of merit of 16 fJ/conversion step.