A Robust BBPLL-Based 0.18- μm CMOS Resistive Sensor Interface With High Drift Resilience Over a −40 ◦C–175 ◦C

Abstract

This paper presents a drift-resilient time-based resistive sensor interface in a 0.18- µm CMOS technology. The interface is built around only two oscillators, a phase detector, a digital filter, and a digital-to-analog converter (DAC), resulting in a simple first-order Delta–Sigma design with a predictable transfer function. The highly digital approach not only results in a small area but also implies that only a few analog circuits are sensitive to drift. The holisti c drift-resilience strategy imple- mented combines time-based chopping and voltage-controlled oscillator (VCO) tuning to remove the dc and low-frequency errors introduced by VCO nonidealities and drift. These tech- niques do not introduce a significant area and power over- head. Silicon measurements show that the proposed bang–bang phase-locked loop (BBPLL)-based sensor interface exhibits ppm-level gain drift and offset drift for the entire −40 ◦C–175 ◦C temperature range while using a single-temperature calibration scheme and no external accurate references nor components for this drift stability. The interface provides a 15-effective number of bits conversion for a 100-ms conversion time and consumes 3.41 mW of power and occupies only 0.23 mm 2 of the active area.