JSSC 2019第7期Memory28nmSRAM

An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Opera

提出一种带片上动态可靠性管理的8T SRAM，通过两阶段写操作解决BTI退化问题。

28nm FDSOI, 16-kb SRAM, 3.42%功耗开销, 10%面积开销

SRAMBTI退化动态可靠性管理两阶段写操作FDSOI

▸片上动态可靠性管理：通过智能监测和缓解由BTI退化引起的半选单元稳定性故障，实现动态可靠性管理。该方法利用基于复制行的BTI感知稳定性监测器，实时调整写字线电压水平，显著降低故障率（从57.13%降至0%）。

▸BTI感知写字线控制：采用自动化BTI感知写字线控制技术，动态检测SRAM单元的BTI退化情况，并通过调整写字线电压水平来优化单元稳定性。该方法在28nm FDSOI技术上验证，仅增加3.42%的功耗和10%的面积开销。

▸两阶段写操作（TPWO）：通过将写字线电压水平分为两个阶段，在不影响其他电路参数的情况下，有效维持半选单元的稳定性。这一创新方法显著提升了SRAM的可靠性和寿命，适用于深纳米工艺。

Abstract

Bias temperature instability (BTI) degradation poses increasingly critical lifetime reliability design challenges in static random access memory (SRAM), as fabrication technology marches toward a very deep nanometer regime. This paper presents circuit techniques that enable on-chip dynamic relia- bility management, which intelligently monitors and mitigates the half-selected cell stability failure due to BTI degradation in SRAM. The dynamic reliability management is achieved through the automate