← 返回 JSSC 论文列表JSSC 2019第8期Clocking & PLLs65nmPLL
A 0016 mm 2 026-μWMHz 60240-MHz Digital PLL With Delay-Modulating Clock Buffer i
本文提出了一种新型数字PLL设计，结合RC振荡器和环形振荡器的优势，适用于超低功耗MCU和IoT应用。
65nm CMOS, 50–300 MHz输出频率, 超低功耗
数字PLL超低功耗RC振荡器环形振荡器IoT
▸使用延迟调制时钟缓冲器实现比例控制
▸采用低面积数模转换器实现数字控制振荡器
▸结合RC振荡器和环形振荡器的互补优势
Abstract
Ultra-low-power systems, such as wearables and
Internet-of-Things (IoT), require power- and volume-efficient
micro-controller units (MCUs) capable of operating across a
wide range of frequencies under extreme power constraints. This
paper presents the techniques to implement clock generators that
cater to the needs of such MCUs and other similar ultra-low-
power applications. RC relaxatio n oscillators (RCOs) are shown
to achieve excellent frequency stability when generating clocks
in kilohertz t