JSSC 2019第8期Clocking & PLLs55nmPLLProcessor/CPU

An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling an

提出一种基于指令驱动的自适应时钟管理方案，通过动态相位缩放和编译器辅助设计实现低功耗微处理器。

55-nm CMOS, 20%性能提升, 32%能耗节省

自适应时钟管理动态相位缩放编译器辅助设计ARMv7 ISA低功耗微处理器

▸指令级时序变化的动态相位缩放（DPS）操作

▸编译器辅助的跨层设计方法

▸指令时序校准方案以应对PVT变化

Abstract

This paper presents an instruction-driven adaptive clock management scheme using a dynamic phase scaling (DPS) operation and compiler-assisted cross-layer design methodol- ogy for a low power microprocessor. The intrinsic instruction- level timing variation is explored on an ARMv7 ISA pipeline architecture. The clock period can be dynamically adjusted by a multi-phase all-digital PLL, with the timing encoded into the instruction set at the compiler level. Special compiler optimiza- tion schemes