JSSC 2019第8期Digital Circuits65nmNeural Network Accelerator

Self-Timed Pulsed Latch for Low-V oltage Operation With Reduced Hold Time

提出了一种自定时脉冲锁存器，用于低电压操作，显著减少保持时间。

65nm CMOS, 300mV降低, 77%保持时间减少

自定时脉冲锁存器低电压操作保持时间时序开销65nm工艺

▸创新点1：自适应生成透明窗口（方法创新）。通过实时比较输入和输出信号，动态调整透明窗口的开启时机，解决了传统脉冲锁存器因固定窗口导致的时序冲突问题，显著提升了低电压下的时序容限。

▸创新点2：显著减少保持时间（电路创新）。采用自定时机制优化锁存器内部反馈路径，实测保持时间降低77%（65nm工艺），有效缓解了高速电路中的时序收敛压力。

▸创新点3：突破性降低工作电压（系统创新）。通过消除主从触发器结构固有的建立时间问题，将最低工作电压降低300mV至0.6V，输入输出延迟较MSFF结构减少45%，大幅提升能效比。

▸创新点4：时序开销优化（电路创新）。独特的自定时架构避免了传统主从触发器级联带来的双倍时钟延迟，在0.6V下实现更短的组合逻辑有效周期，提升系统整体吞吐量。

Abstract

A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show th