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A 1-V 175- μW 946-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented
采用65nm CMOS工艺的1V 175μW ΔΣ调制器，实现94.6dB SNDR和25kHz带宽。
65nm CMOS, 1V, 5MS/s, 175μW, 94.6dB SNDR, 25kHz带宽
ΔΣ调制器分段积分CMOS低功耗高SNDR
▸分段积分技术实现前两个积分器
▸结合逆变器和源耦合对运算放大器以提升性能并节省功耗
▸第一积分器在输出采样时降低工作速度以进一步减少功耗
Abstract
A 2-1 multistage noise-shaping (MASH) switched-
capacitor (SC) delta-sigma modulator (DSM) was fabricated
using a 65-nm CMOS technology. We developed two separate seg-
mented integration techniques to implement the first two integra-
tors in the DSM. The techniques use both an inverter (IVT)-based
opamp and a source-coupled-pair (SCP)-based opamp to relay
the charge integration operation. This increases performance
while saving power. The first integrator also operates more slowly
during output sa