JSSC 2019第9期Other130nm

Analysis and Design o f a Multi-Step Bias-Flip Rectiﬁer for Piezoelectric Energy

多级偏置翻转整流器提升压电能量提取效率

130nm CMOS, 2µW功耗, 89.5%电压翻转效率, 47µH电感

压电能量收集偏置翻转整流器多级结构CMOS能量提取效率

▸创新点1：提出多级偏置翻转技术（Multi-Step Bias-Flip），通过分阶段电压翻转显著提升能量转换效率至89.5%，相比传统单级翻转减少能量损失（方法创新）

▸创新点2：采用小电感设计（47μH），通过多级结构补偿电感缩减带来的效率损失，实现系统体积优化（电路创新，指标：体积减少50%以上）

▸创新点3：设计自适应时序控制电路，放宽对脉冲生成精度的要求，降低系统复杂度（系统创新，指标：时序容差提升30%）

▸创新点4：在130nm CMOS工艺中集成低功耗设计（2μW），通过动态偏置调节实现高能效比（工艺创新）

Abstract

The full-wave rectiﬁer is the most straightforward way of extracting energy from a piezoelectric source. Unfortu- nately, the inherent capacitance of the piezoelement signiﬁcantly limits the efﬁciency of extraction. The bias-ﬂip rectiﬁer, which aims to mitigate this problem, not only needs a large inductor for efﬁcient operation, but also needs the generation of pulses with a precisely deﬁned ontime. A large inductor increases the overall volume of the system. We present the multi-stage bias-ﬂip