Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM

Abstract

We present the architectural, circuit topology, transistor-level schematics, and layout design considerations for the highest sampling-rate single-chip ADC reported to date in any semiconductor technology. The circuit uses a 2 × time-interleaved architecture integrating two track-and-hold amplifiers, each driving a 5-bit flash sub-ADC sampled at 64 GHz in antiphase. For testing purposes, the chip also incorporates a time-interleaved 128-GS/s thermometer-coded 5-bit current steering DAC. The performance of the ADC-DAC combo, including the SFDR and the effective number of bits of 4 bits up to 32-GHz input signals, was characterized on die and includes the impact of the DAC. The power consumption and layout footprint of the ADC, critical for operation at 128 GS/s, were minimized by employing novel 1-mA Cherry-Hooper comparators and quasi-current-mode logic MOS-HBT latches with active peaking, which reduced the foot- print of each of the 64 ADC-lanes to 10 µm × 70 µm. The total power consumption of the ADC is 1.25 W and the total die area of the ADC-DAC chip is 1.1 mm × 1.9 mm.