Reconfigurable Clock Networks for Wide V oltage Scaling

Abstract

In this paper, reconfigurable clock networks for adaptation from nominal voltage down to sub-threshold volt- ages are presented. Indeed, clock network design tradeoffs at near- and sub-threshold voltages substantially differ from above- threshold voltages, due to the very different balance between clock repeater and wire delay. In the proposed reconfigurable clock network scheme, the number of repeater levels is dynam- ically adapted to the supply voltage to mitigate the clock skew degradation across a wide voltage range. At nominal voltage, the number of repeater levels is adjusted to a higher value to mitigate the important clock skew contribution of wires. At lower voltages, it is progressively lowered to mitigate the dominant clock skew contribution of clock buffers. The proposed approach is demonstrated on a 256-point complex fast Fourier transform (FFT) processor test chip in 40 nm, and a standalone clock tree to statistically characterize the skew. Measurements show that the proposed reconfigurable clock network reduces clock skew by up to 3.3×, enabling 110-mV V min reduction and 31% minimum energy reduction at 1.8% area penalty, compared to traditional fixed clock networks.