← 返回 JSSC 论文列表JSSC 2019第10期Clocking & PLLs28nmCDR
A 10-Gbs 003-mm 2 128-pJbit Half-Rate Injection-Locked CDR With Path Mismatch Tr
提出一种带路径失配跟踪环路的10Gb/s半速率全数字注入锁定时钟数据恢复电路
28nm CMOS, 0.9V, 10Gb/s, 12.8mW, 0.03mm²
时钟数据恢复注入锁定全数字电路路径失配抖动容限
▸采用路径失配跟踪环路优化注入脉冲路径延迟
▸通过相位检测器错误信息与数据转换极性关联实现鲁棒注入
▸在路径延迟失配情况下仍保持良好抖动容限性能
Abstract
A 10-Gb/s, 0.03-mm 2, 1.28-pJ/bit half-rate all-
digital injection-locked clock and data recovery (ILCDR) with a
path mismatch tracking (PMT) loop is presented. When injection
timing is not perfectly aligned with the phase of the oscillator ,
the timing margin of the data sampler is reduced, resulting in
the degradation of jitter tolerance (JTOL) performance. The
proposed ILCDR achieves robust injection behavior over path
mismatch variations by correlating the error information from
the phase de