A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals Y u-Zhe Wang, Y ao-Pin Wang, Yi-Chung Wu , Student Member , IEEE, and Chia-Hsiang Y ang , Senior Member , IEEE

Abstract

This article presents a reconfigurable processor based on the alternating direction method of multipliers (ADMM) algorithm for reconstructing compressively sensed physiological signals. The architecture is flexible to support physiological ExG [electrocardiography (ECG), electromyography (EMG), and elec- troencephalography (EEG)] signal with various signal dimensions (128, 256, 384, and 512). Data cha racteristics are utilized to substantially reduce the overall hardware complexity by up to 99%. A 16 × folded architecture achieves a 64% area-power product reduction compared with the unfolded one. A customized buffer is used for multi-word access, which reduces data latency by four times. It dissipates 75% less power with only 25% area when compared with the realization with conventional flip-flops. As a proof of concept, a reconfigurable processor for recon- structing ExG signals is presented. Fabricated in a 40-nm CMOS technology, the processor integrates 3.69-M gates in 3.23 mm 2. The chip delivers a throughput of 573–2901 kSamples/s (kS/s) for ExG signals and dissipates less than 12.6 mW at 87 MHz from a 0.60-V supply. Compared with state-of-the-art designs, the chip achieves a 1.5-to-14× higher throughput with 3.2-to-11× less energy, given the performance specification [reconstruction signal-to-noise ratio (RSNR) ≥ 15 dB].