A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

Abstract

This paper demonstrates a signal analysis system- on-chip (SoC) consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the application core and the accelerators are design instances produced through an agile design-space exploration process by generators that allow for a wide range of parameter configurations. The signal processing chain consists of generated instances of a time-interleaved analog-to-digital converter (ADC) followed by a digital tuner, a finite-impulse response (FIR) filter, a polyphase filter, and a fast Fourier transform (FFT) all connected to the five-stage, in-order RISC-V Rocket processor via an AXI4 bus. The generator-based design methodology is detailed, along with the agile design process of producing the fabricated design instance. The 5 mm × 5m m chip is implemented in a 16-nm FinFET process and operates at 410 MHz at 750 mV drawing 600 mW. Presented applications show coupled functionality of the application processor and accel- erator performing spectrometry and radar receive processing, and a comparison with other state-of-the-art application-specific integrated circuits (ASICs) proves that generators can produce performance-competitive designs. Manuscript received January 29, 2019; revised May 5, 2019; accepted June 6, 2019. Date of publication July 17, 2019; date of current version Sep- tember 24, 2019. This paper was approve d by Guest Editor Chen-Hao Chang. This work was supported i