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JSSC 2019第10期Digital Circuits65nmNeural Network Accelerator

An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dyna

提出一种基于时间域的神经网络加速器,采用动态阈值误差校正技术,实现高效能计算。
104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC
神经网络加速器时间域计算动态阈值误差校正低功耗SRAM阵列
使用一次性延迟测量技术
动态阈值误差校正(DTEC)
基于SRAM阵列的延迟累积计算MAC操作
Abstract
As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low- power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inver