JSSC 2019第10期Other

Fourier transform. Pipeline registers favor the direct-form FFT slightly, though the critical path through this circuit is still through log 2(n) butterﬂies, so one pipeline register per stage (a pipeline depth of log 2(n)) is recommended. Bitwidths grow immediately to the estimated output bitwidth assuming one bit growth per stage. This growth is split between the biplex and direct FFT stages, so bitwidth growth happens twice. If the output has more or fewer bits than normal growth would imply, the result is automatically truncated or sign- extended as needed. This archit ecture reuses signiﬁcantly from

该论文探讨了傅里叶变换流水线寄存器的优化设计及其在混合信号模块集成中的应用。

1.2-GHz clock, 8-bit words, deserialized by a factor of 4

傅里叶变换流水线寄存器混合信号ADC高速信号处理

▸创新点1：流水线寄存器优化设计（方法创新）。论文提出了一种基于对数级数（log2(n)）的流水线寄存器分配策略，每级FFT阶段仅需一个流水线寄存器，显著减少了硬件资源消耗，同时保证了信号处理的时序正确性。

▸创新点2：混合信号模块集成（系统创新）。通过Chisel语言将ADC作为模拟黑盒集成，实现了数字与模拟模块的高效协同设计，支持仿真与物理设计的无缝切换，简化了混合信号系统的开发流程。

▸创新点3：高速信号处理路径避免（电路创新）。采用4倍解串器将1.2GHz高速ADC输出降频至300MHz，避免了高频信号路径的设计挑战，同时通过32路并行处理维持数据吞吐量，降低了功耗与时序收敛难度。

▸创新点4：可编程SRAM校准技术（电路创新）。利用运行时可配置的SRAM存储校准数据，支持多种工作模式（如直接存储ADC样本），增强了系统测试灵活性，并实现了硬件资源复用。

Abstract

ll through log 2(n) butterﬂies, so one pipeline register per stage (a pipeline depth of log 2(n)) is recommended. Bitwidths grow immediately to the estimated output bitwidth assuming one bit growth per stage. This growth is split between the biplex and direct FFT stages, so bitwidth growth happens twice. If the output has more or fewer bits than normal growth would imply, the result is automatically truncated or sign- extended as needed. This archit ecture reuses signiﬁcantly from the previous s