← 返回 JSSC 论文列表JSSC 2019第11期Power Management65nmPLLDLL
A 16-to-30-GHz Fractional- N MDLL With a Digital-to-Time Converter Range-Reducti
提出一种采用DTC范围缩减技术的16至30GHz分数N MDLL，优化了抖动与功耗的平衡。
65nm CMOS, 1.6-to-3.0GHz, 397fs rms jitter, 2.5mW, -244dB FoM
分数N MDLL数字时间转换器抖动优化亚采样CMOS
▸数字时间转换器（DTC）范围缩减技术
▸亚采样bang-bang相位检测器
▸优化的抖动-功耗权衡设计
Abstract
This article analyzes the jitter-power tradeoff in
multiplying delay-locked loops (MDLLs), which differs from the
more typical phase-locked loop one, and identifies a design opti-
mization criterion. The methodology is applied to a fractional-
N MDLL with a sub-sampling bang-bang phase detector and a
novel digital-to-time converter (DTC) range-reduction technique,
which limits the jitter added to the reference signal, at no
additional power penalty. The prototype has been implemented
in 65-nm CMO