JSSC 2019第11期Wireline I/O16nmPAM-4Neural Network Accelerator

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gbs λ PAM-4 Optica

一款16nm FinFET CMOS工艺的线性TIA，支持100Gbs PAM-4光链路，具有高带宽、低噪声和低功耗特性。

16nm FinFET CMOS, 60.8mW功耗, 27GHz带宽, 16.7pA/√Hz输入噪声密度

跨阻放大器PAM-4FinFET动态电压缩放高线性度

▸采用dc耦合CMOS反相器实现全信号路径

▸动态电压缩放技术以应对PVT变化

▸可编程跨阻（62至83dBΩ）支持数字自动增益控制

Abstract

A linear transimpedance ampliﬁer (TIA) for a 53 GBd PAM-4 optical link to support 100 Gb/s data on a single wavelength is reported. Designed in a 16 nm FinFET CMOS process, the chip consumes 60.8 mW with <2% total harmonic distortion (THD), while producing a 600 mV pk− pk differential output, a − 3 dB bandwidth of 27 GHz, and an input referred noise density of 16.7 pA/ √ Hz. Transimpedance can be programed from 62 to 83 dB in 0.5 dB steps to enable digital automatic gain control. Novel circui