An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor Xun Sun , Student Member , IEEE, Fahim ur Rahman , Student Member , IEEE, V enkata

Abstract

Traditional digital systems employ independent loops to control supply voltage ( Vdd) and clock frequency ( fclk). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concur- rently, a voltage regulation loop sets V dd to a target value under rapidly varying load current or line-side disturbances. Limita- tions in voltage regulator loop bandwidth result in significant V dd fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful V dd guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts fclk to Vdd and T variations, requiring minimal guardbands. UniCaP absorbs Vdd control into the clock regulation loop, using it to adjust fclk and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive Vdd guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microprocessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average V dd guardband reduction, without any performance loss from adaptive clocking, and temperature margin reduct