Dual-Tap Computational Photography Image Sensor With Per-Pixel Pipelined Digital Memory for Intra-Frame Coded Multi-Exposure

Abstract

A coded-exposure-pixel image sensor for compu- tational imaging applications is presented. Each frame expo- sure time is divided into N subframes. Within each subframe, each pixel sorts photo-generated charge into two charge taps depending on that pixel’s 1-bit binary code. N global updates of arbitrary pixel-wise codes are implemented in each frame to enable N short global pixel-specific subexposures within one frame. To make these subexposures global, two latches per pixel are utilized in a pipelined fashion. The code for the next subframe is loaded into latch 1 in a row parallel fashion, while the code for the current subframe is being applied by latch 2 globally for photo-generated charge sorting during the current subexposure. A 280 H × 176V image sensor prototype with 11 .2-µm pixel pitch has been fabricated in a 0 .11-µm CMOS image sensor (CIS) technology. The image sensor has been demonstrated in two computational photography applications, each using only a single frame of a video: 1) computing both Manuscript received April 25, 2019; revised July 2, 2019; accepted July 20, 2019. Date of publication September 18, 2019; date of current version October 23, 2019. This article was approved by Associate Editor Vivek De. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under RGP IN, RTI, and SGP programs, in part by DARPA under REVEAL Program, and in part by CMC Microsystems. (Corresponding author: Navid Sarhangnejad.) N. Sar